(1) Technical Field
This invention relates to integrated circuit die seal structures for electronic circuits, and particularly to integrated circuit die seal structures for RF circuits.
(2) Background
As is known in the field of integrated circuit (IC) fabrication, a semiconductor die (also known as a “chip”) may include a die seal. A die seal is generally an electrically conductive ring integrally formed as part of a die at or near an outer edge region of a circuit-bearing planar surface of the die designed to protect the integrated circuit from contaminants that may affect the die yield during processing and affect performance of a chip after the chip has been fabricated, and to make the die less susceptible to mechanical stress caused by a die saw. Some IC implementation technologies, such as CMOS, are especially prone to contamination, and thus generally include a die seal. In CMOS-based RF circuits, it is common to make the die seal floating (i.e., having no electrical connection).
FIG. 1 is a top view of one example of a prior art stylized integrated circuit die 100 having a peripheral die seal 102. The illustrated example includes a two-port radio frequency (RF) single-pole, double-throw (SPDT) switch as an illustrative circuit. A common port CP may be selectively coupled to either port P1 or to port P2 by closing a corresponding switch SW1 or SW2, which are typically implemented as field effect transistors (FETs) controlled by other circuitry (not shown); for simplicity, the switches SWn are shown schematically rather than as physical structures on the IC die 100. As is known, a FET switch behaves as a low impedance resistor when closed, and as a capacitor when open.
The ports CP, P1, P2 are typically electrically conductive connection regions or pads placed adjacent an edge of the IC die 100 to facilitate connection to electrically conductive bonding pads (which may be on the other side of the IC die 100, connected by vias) for further connection to external circuitry, such as by wire bonding or flip-chip solder bumps. In order to improve isolation of the various circuit components (e.g., the switches SWn and ports) from each other, the components are typically spaced from each other around the periphery of the die 100, but within the die seal 102. In addition, it is common to place ground pads G along the edges of the IC die 100 to facilitate coupling internal circuit elements through corresponding electrically conductive bonding pads to an external circuit ground.
One application for the illustrated IC die 100 is in a radio system. For example, the common port CP may be connected to an antenna, an RF transmitter circuit may be connected to port P1, and an RF receiver circuit may be connected to port P2. However, for RF circuits operating at high frequencies (equal to or greater than about 10 GHz), the die seal 102 can couple the fundamental energy emanating from activated internal circuitry and re-route such energy to unwanted signal paths, which can subsequently degrade key performance parameters (e.g., isolation, insertion loss, receiver sensitivity, etc.).
FIG. 2 is a top view of the example from FIG. 1 of a prior art stylized integrated circuit die 100 having a peripheral die seal 102, and showing energy flow in an intended signal path and in an unintended signal path. In the illustrated configuration, FET switch SW1 is open (thus behaving as a capacitor, as indicated by the equivalent circuit element representation), decoupling the common port CP from port P1; conversely, FET switch SW2 is closed (thus behaving as a low impedance resistor, as indicated by the equivalent circuit element representation), coupling the common port CP to port P2. If the common port CP is coupled to an external antenna and port P2 is coupled to an RF receiver circuit, RF electromagnetic energy picked up by the antenna would flow along the intended signal path from the common port CP to the receiver port P2, as indicated by the arrow 200. However, that RF electromagnetic energy is inductively coupled to the floating die seal 102 and induces an opposite flow of parasitic energy around the entire die seal 102, as indicated by the arrow 202. The parasitic energy carried by die seal 102 then induces an opposite and unintended flow of parasitic energy in the signal path from the nominally decoupled port P1 to the common port CP, as indicated by the arrow 204. The parasitically coupled energy from the die seal 102 thus generally degrades the isolation between the signal ports P1 and P2.
Accordingly, there is a need for an integrated circuit structure for RF circuits that mitigates the effects of parasitic coupling through a die seal. The present invention meets this need.